The literature I got was very exciting, though some of it, predictably, is over my head. The level of explication in what
I saw made it hard for me to tell whether the local processors had enough cache memory (or enough general registers) to minimize
contention on the bus when you hang a significant number (think of 10 to the second power . . . . ) processors on it.
But thank you.
I certainly enjoyed our conversation; and whuther [sic] we can conveniently rejoin in SFO on 8/17, I hope we intersect again